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As an example, taking the case of 64 MBs, if the oscillator and peripheral clock
frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per
bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor
equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral
and oscillator clock frequencies should be at least 2.
45.4.9 Clock domains and restrictions
The FlexCAN module has two clock domains asynchronous to each other:
• The Bus Domain feeds the Control Host Interface (CHI) submodule and is derived
from the peripheral clock.
• The Oscillator Domain feeds the CAN Protocol Engine (PE) submodule and is
derived directly from a crystal oscillator clock, so that very low jitter performance
can be achieved on the CAN bus.
When CTRL1[CLKSRC] bit is set, synchronous operation occurs because both domains
are connected to the peripheral clock (creating a 1:1 ratio between the peripheral and
oscillator domain clocks).
When the two domains are connected to clocks with different frequencies and/or phases,
there are restrictions on the frequency relationship between the two clock domains. In the
case of asynchronous operation, the Bus Domain clock frequency must always be greater
than the Oscillator Domain clock frequency.
NOTE
Asynchronous operation with a 1:1 ratio between peripheral
and oscillator clocks is not allowed.
45.4.10 Modes of operation details
The FlexCAN module has functional modes and low-power modes. See Modes of
operation for an introductory description of all the modes of operation. The following
sub-sections contain functional details on Freeze mode and the low-power modes.
CAUTION
“Permanent Dominant” failure on CAN Bus line is not
supported by FlexCAN. If a Low-Power request or Freeze
mode request is done during a “Permanent Dominant”, the
corresponding acknowledge can never be asserted.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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