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45.4.10.1 Freeze mode

This mode is requested by the CPU through the assertion of the HALT bit in the MCR

the FRZ bit is asserted in the MCR Register and the module is not in a low-power mode.

The acknowledgement is obtained through the assertion by the FlexCAN of FRZ_ACK

bit in the same register. The CPU must only consider the FlexCAN in Freeze mode when

both request and acknowledgement conditions are satisfied.

When Freeze mode is requested during transmission or reception, FlexCAN does the

following:

• Waits to be in either Intermission, Passive Error, Bus Off or Idle state

• Waits for all internal activities like arbitration, matching, move-in and move-out to

finish. A pending move-in is not taken into account.

• Ignores the Rx input pin and drives the Tx pin as recessive

• Stops the prescaler, thus halting all CAN protocol activities

• Grants write access to the Error Counters Register, which is read-only in other modes

• Sets the NOT_RDY and FRZ_ACK bits in MCR

After requesting Freeze mode, the user must wait for the FRZ_ACK bit to be asserted in

MCR before executing any other action, otherwise FlexCAN may operate in an

unpredictable way. In Freeze mode, all memory mapped registers are accessible, except

for CTRL1[CLK_SRC] bit that can be read but cannot be written.

Exiting Freeze mode is done in one of the following ways:

• CPU negates the FRZ bit in the MCR Register

• The MCU is removed from Debug Mode and/or the HALT bit is negated

The FRZ_ACK bit is negated after the protocol engine recognizes the negation of the

freeze request. When out of Freeze mode, FlexCAN tries to re-synchronize to the CAN

bus by waiting for 11 consecutive recessive bits.

Functional description

K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

1174

Preliminary

Freescale Semiconductor, Inc.

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