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45.4.10.2 Module Disable mode
This low power mode is normally used to temporarily disable a complete FlexCAN
block, with no power consumption. It is requested by the CPU through the assertion of
the MDIS bit in the MCR Register and the acknowledgement is obtained through the
assertion by the FlexCAN of the LPM_ACK bit in the same register. The CPU must only
consider the FlexCAN in Disable mode when both request and acknowledgement
conditions are satisfied.
If the module is disabled during Freeze mode, it requests to disable the clocks to the PE
and CHI sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the
module is disabled during transmission or reception, FlexCAN does the following:
Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and then checks it to be recessive
Waits for all internal activities like arbitration, matching, move-in and move-out to
finish. A pending move-in is not taken into account.
Ignores its Rx input pin and drives its Tx pin as recessive
Shuts down the clocks to the PE and CHI sub-modules
Sets the NOTRDY and LPMACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped
registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask
Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx
FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and
the reserved words within RAM may not be accessed when the module is in Disable
Mode. Exiting from this mode is done by negating the MDIS bit by the CPU, which
causes the FlexCAN to request to resume the clocks and negate the LPM_ACK bit after
the CAN protocol engine recognizes the negation of disable mode requested by the CPU.
45.4.10.3 Stop mode
This is a system low-power mode in which all MCU clocks can be stopped for maximum
power savings. The Stop mode is globally requested by the CPU and the
acknowledgement is obtained through the assertion by the FlexCAN of a Stop
Acknowledgement signal. The CPU must only consider the FlexCAN in Stop mode when
both request and acknowledgement conditions are satisfied.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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