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If FlexCAN receives the global Stop mode request during Freeze mode, it sets the
LPMACK bit, negates the FRZACK bit and then sends the Stop Acknowledge signal to
the CPU, in order to shut down the clocks globally.
If Stop mode is requested during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to
finish. A pending move-in is not taken into account.
• Ignores its Rx input pin and drives its Tx pin as recessive
• Sets the NOTRDY and LPMACK bits in MCR
• Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks
globally
Stop mode is exited when the CPU resumes the clocks and removes the Stop Mode
request. This can be as a result of the Self Wake mechanism.
In the Self Wake mechanism, if the SLFWAK bit in MCR Register was set at the time
FlexCAN entered Stop mode, then upon detection of a recessive to dominant transition
on the CAN bus, FlexCAN sets the WAKINT bit in the ESR Register and, if enabled by
the WAKMSK bit in MCR, generates a Wake Up interrupt to the CPU. Upon receiving
the interrupt, the CPU should resume the clocks and remove the Stop mode request.
FlexCAN will then wait for 11 consecutive recessive bits to synchronize to the CAN bus.
As a consequence, it will not receive the frame that woke it up. The following table
details the effect of SLFWAK and WAKMSK upon wake-up from Stop mode. Note that
wake-up from Stop mode only works when both bits are asserted.
After the CAN protocol engine recognizes the negation of the Stop mode request, the
FlexCAN negates the LPMACK bit.
Table 45-82. Wake-up from Stop Mode
SLFWAK WAKINT WAKMSK
MCU
clocks enabled
Wake-up interrupt
generated
0 - - No No
0 - - No No
1 0 0 No No
1 0 1 No No
1 1 0 No No
1 1 1 Yes Yes
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1176
Preliminary
Freescale Semiconductor, Inc.
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