Information

• Determine the bit rate by programming the PRESDIV field
• Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers
• The Control and Status word of all Message Buffers must be initialized
• If Rx FIFO was enabled, the ID filter table must be initialized
• Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
MCR Register for Wake-Up interrupt and in CTRL Register (for Bus Off and Error
interrupts)
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
Initialization/application information
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1180
Preliminary
Freescale Semiconductor, Inc.
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