Information

Baud Rate, Delay &
Transfer Control
Shift Register
SPI
SCK
S PI
32
Data
Data
TX FIFO
Slave Bus Interface
Clock/Reset
POPR
eDMA
INTC
DMA and Interrupt Control
PUSHR
RX FIFO
CMD
32
8
PCS[x]/SS
SIN
SOUT
Figure 46-1. SPI Block Diagram
46.1.2 Features
The module supports the following features:
• Full-duplex, three-wire synchronous transfers
• Master and Slave modes:
• Data streaming operation in Slave mode with continuous slave selection
• Buffered transmit operation using the transmit first in first out (TX FIFO) with depth
of four entries
• Buffered receive operation using the receive FIFO (RX FIFO) with depth of four
entries
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI
queues
Introduction
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1182
Preliminary
Freescale Semiconductor, Inc.
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