Information

46.1.3 Module Configurations
The module supports SPI configuration.
46.1.3.1 SPI Configuration
The SPI configuration allows the module to send and receive serial data. This
configuration allows the module to operate as a basic SPI block with internal FIFOs
supporting external queue operation. Transmitted data and received data reside in
separate FIFOs. The host CPU or a DMA controller read the received data from the
Receive FIFO and write transmit data to the Transmit FIFO.
For queued operations, the SPI queues can reside in system RAM, external to the module.
Data transfers between the queues and the module FIFOs are accomplished by a DMA
controller or host CPU. The following figure shows a system example with DMA, DSPI,
and external queues in system RAM.
System RAM
DSPI
DMA Controller
TX Queue
RX FIFO
TX FIFO
Shift Register
Addr/Ctrl
RX Queue
Addr/Ctrl
Req
T
Done
Tx Data
Rx Data
Rx Data
Tx Data
or host CPU
Figure 46-2. SPI with queues and DMA
46.1.4 Modes of Operation
The module supports the following modes of operation that can be divided into two
categories:
• Module-specific modes:
• Master mode
Introduction
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1184
Preliminary
Freescale Semiconductor, Inc.
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