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46.1.4.5 Debug Mode
Debug mode is used for system development and debugging. The MCR[FRZ] bit controls
module behavior in the Debug mode:
• If the bit is set, the module stops all serial transfers, when the MCU is in debug
mode.
• If the bit is cleared, the MCU debug mode has no effect on the module.
46.2 Module signal descriptions
This section provides description of the module signals.
The following table lists the signals that may connect off chip depending on device
implementation.
Table 46-1. Module signal descriptions
Signal Master Mode Slave Mode Port Direction
PCS0/SS Peripheral Chip Select 0 output Slave Select input I/O
PCS[3:1] Peripheral Chip Select 1 – 3 Unused O
PCS4 Peripheral Chip Select 4 Unused O
SIN Serial Data In I
SOUT Serial Data Out O
SCK Master mode: Serial Clock (output) Serial Clock (input)
I/O
46.2.1 PCS0/SS — Peripheral Chip Select/Slave Select
In Master mode, the PCS0 signal is an output that selects which slave device the current
transmission is intended for.
In Slave mode, the active low SS signal is an input signal that allows an SPI master to
select the module as the target for transmission.
46.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3
PCS1 – PCS3 are output signals in Master mode.
In Slave mode, these signals are unused.
Module signal descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1186
Preliminary
Freescale Semiconductor, Inc.
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