Information

46.2.3 PCS4 — Peripheral Chip Select 4
In Master mode, PCS4 is an output signal.
In Slave mode, this signal is unused.
46.2.4 SIN — Serial Input
SIN is a serial data input signal.
46.2.5 SOUT — Serial Output
SOUT is a serial data output signal.
46.2.6 SCK — Serial Clock
SCK is a serial communication clock signal. In Master mode, the module generates the
SCK. In Slave mode, SCK is an input from an external bus master.
46.3 Memory Map/Register Definition
Register accesses to memory addresses that are reserved or undefined result in a transfer
error. Write access to the POPR also results in a transfer error.
SPI memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C000 Module Configuration Register (SPI0_MCR) 32 R/W 0000_4001h 46.3.1/1190
4002_C008 DSPI Transfer Count Register (SPI0_TCR) 32 R/W 0000_0000h 46.3.2/1193
4002_C00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR0)
32 R/W 7800_0000h 46.3.3/1193
4002_C00C
DSPI Clock and Transfer Attributes Register (In Slave Mode)
(SPI0_CTAR0_SLAVE)
32 R/W 7800_0000h 46.3.4/1198
4002_C010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI0_CTAR1)
32 R/W 7800_0000h 46.3.3/1193
4002_C02C DSPI Status Register (SPI0_SR) 32 R/W 0201_0000h 46.3.5/1200
Table continues on the next page...
Chapter 46 Serial Peripheral Interface (SPI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1187
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