Information

SPI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI0_RSER)
32 R/W 0000_0000h 46.3.6/1203
4002_C034
DSPI PUSH TX FIFO Register In Master Mode
(SPI0_PUSHR)
32 R/W 0000_0000h 46.3.7/1205
4002_C034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI0_PUSHR_SLAVE)
32 R/W 0000_0000h 46.3.8/1207
4002_C038 DSPI POP RX FIFO Register (SPI0_POPR) 32 R 0000_0000h 46.3.9/1207
4002_C03C DSPI Transmit FIFO Registers (SPI0_TXFR0) 32 R 0000_0000h
46.3.10/
1208
4002_C040 DSPI Transmit FIFO Registers (SPI0_TXFR1) 32 R 0000_0000h
46.3.10/
1208
4002_C044 DSPI Transmit FIFO Registers (SPI0_TXFR2) 32 R 0000_0000h
46.3.10/
1208
4002_C048 DSPI Transmit FIFO Registers (SPI0_TXFR3) 32 R 0000_0000h
46.3.10/
1208
4002_C07C DSPI Receive FIFO Registers (SPI0_RXFR0) 32 R 0000_0000h
46.3.11/
1208
4002_C080 DSPI Receive FIFO Registers (SPI0_RXFR1) 32 R 0000_0000h
46.3.11/
1208
4002_C084 DSPI Receive FIFO Registers (SPI0_RXFR2) 32 R 0000_0000h
46.3.11/
1208
4002_C088 DSPI Receive FIFO Registers (SPI0_RXFR3) 32 R 0000_0000h
46.3.11/
1208
4002_D000 Module Configuration Register (SPI1_MCR) 32 R/W 0000_4001h 46.3.1/1190
4002_D008 DSPI Transfer Count Register (SPI1_TCR) 32 R/W 0000_0000h 46.3.2/1193
4002_D00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI1_CTAR0)
32 R/W 7800_0000h 46.3.3/1193
4002_D00C
DSPI Clock and Transfer Attributes Register (In Slave Mode)
(SPI1_CTAR0_SLAVE)
32 R/W 7800_0000h 46.3.4/1198
4002_D010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI1_CTAR1)
32 R/W 7800_0000h 46.3.3/1193
4002_D02C DSPI Status Register (SPI1_SR) 32 R/W 0201_0000h 46.3.5/1200
4002_D030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI1_RSER)
32 R/W 0000_0000h 46.3.6/1203
4002_D034
DSPI PUSH TX FIFO Register In Master Mode
(SPI1_PUSHR)
32 R/W 0000_0000h 46.3.7/1205
4002_D034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI1_PUSHR_SLAVE)
32 R/W 0000_0000h 46.3.8/1207
4002_D038 DSPI POP RX FIFO Register (SPI1_POPR) 32 R 0000_0000h 46.3.9/1207
4002_D03C DSPI Transmit FIFO Registers (SPI1_TXFR0) 32 R 0000_0000h
46.3.10/
1208
4002_D040 DSPI Transmit FIFO Registers (SPI1_TXFR1) 32 R 0000_0000h
46.3.10/
1208
Table continues on the next page...
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1188
Preliminary
Freescale Semiconductor, Inc.
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