Information

46.3.1 Module Configuration Register (SPIx_MCR)
Contains bits to configure various attributes associated with the module operations. The
HALT and MDIS bits can be changed at any time, but the effect takes place only on the
next frame boundary. Only the HALT and MDIS bits in the MCR can be changed, while
the module is in the Running state.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSTR
CONT_SCKE
DCONF FRZ
MTFE
Reserved
ROOE
Reserved PCSIS[4:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DOZE
MDIS
DIS_
TXF
DIS_
RXF
0 0
SMPL_PT
0 0 0
HALT
W
CLR_TXF
CLR_RXF
Reset
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Memory Map/Register Definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1190
Preliminary
Freescale Semiconductor, Inc.
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