Information

SPIx_MCR field descriptions
Field Description
31
MSTR
Master/Slave Mode Select
Configures the DSPI for either Master mode or Slave mode.
0 DSPI is in Slave mode.
1 DSPI is in Master mode.
30
CONT_SCKE
Continuous SCK Enable
Enables the Serial Communication Clock (SCK) to run continuously.
0 Continuous SCK disabled.
1 Continuous SCK enabled.
29–28
DCONF
DSPI Configuration
Selects among the different configurations of the DSPI.
00 SPI
01 Reserved
10 Reserved
11 Reserved
27
FRZ
Freeze
Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug
mode.
0 Do not halt serial transfers in Debug mode.
1 Halt serial transfers in Debug mode.
26
MTFE
Modified Timing Format Enable
Enables a modified transfer format to be used.
0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
25
Reserved
This field is reserved.
24
ROOE
Receive FIFO Overflow Overwrite Enable
In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwrite
existing data. If the RX FIFO is full and new data is received, the data from the transfer, generating the
overflow, is ignored or shifted into the shift register.
0 Incoming data is ignored.
1 Incoming data is shifted into the shift register.
23–21
Reserved
This field is reserved.
20–16
PCSIS[4:0]
Peripheral Chip Select x Inactive State
Determines the inactive state of PCSx.
0 The inactive state of PCSx is low.
1 The inactive state of PCSx is high.
Table continues on the next page...
Chapter 46 Serial Peripheral Interface (SPI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1191
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