Information

46.4.2.3 FIFO disable operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX
FIFO. The module operates as a double-buffered simplified SPI when the FIFOs are
disabled. The Transmit and Receive side of the FIFOs are disabled separately; setting the
MCR[DIS_TXF] bit disables the TX FIFO, and setting the MCR[DIS_RXF] bit disables
the RX FIFO.
The FIFO disable mechanisms are transparent to the user and to host software. Transmit
data and commands are written to the PUSHR and received data is read from the POPR.
When the TX FIFO is disabled, the fields SR[TFFF], SR[TFUF] and SR[TXCTR] behave
as if there is a one-entry FIFO but the contents of TXFRs, SR[TXNXTPTR] are
undefined. Similarly, when the RX FIFO is disabled, the RFDF, RFOF, and RXCTR
fields in the SR behave as if there is a one-entry FIFO, but the contents of the RXFR
registers and POPNXTPTR are undefined.
46.4.2.4 Transmit First In First Out (TX FIFO) buffering mechanism
The TX FIFO functions as a buffer of SPI data for transmission. The TX FIFO holds four
words, each consisting of SPI data. The number of entries in the TX FIFO is device-
specific. SPI data is added to the TX FIFO by writing to the Data Field of module PUSH
FIFO Register (PUSHR). TX FIFO entries can only be removed from the TX FIFO by
being shifted out or by flushing the TX FIFO.
The TX FIFO Counter field (TXCTR) in the module Status Register (SR) indicates the
number of valid entries in the TX FIFO. The TXCTR is updated every time a 8- or 16-bit
write takes place to the Data Field of SPI_PUSHR or SPI data is transferred into the shift
register from the TX FIFO.
The TXNXTPTR field indicates the TX FIFO Entry that will be transmitted during the
next transfer. The TXNXTPTR field is incremented every time SPI data is transferred
from the TX FIFO to the shift register. The maximum value of the field is equal to the
maximum implemented TXFR number and it rolls over after reaching the maximum.
46.4.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by
writing to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in
the SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controller
indicates that a write to PUSHR is complete. Writing a '1' to the TFFF bit also clears it.
The TFFF can generate a DMA request or an interrupt request. See Transmit FIFO Fill
Interrupt or DMA Request for details.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1212
Preliminary
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