Information

NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
46.4.3.4 Delay after Transfer (t
DT
)
The Delay after Transfer is the minimum time between negation of the PCS signal for a
frame and the assertion of the PCS signal for the next frame. See Figure 46-71 for an
illustration of the Delay after Transfer. The PDT and DT fields in the CTARx registers
select the Delay after Transfer by the formula in the DT field description. The following
table shows an example of how to compute the Delay after Transfer.
Table 46-101. Delay after Transfer computation example
f
SYS
PDT Prescaler DT Scaler Delay after Transfer
100 MHz 0b01 3 0b1110 32768 0.98 ms
NOTE
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
When in Non-Continuous Clock mode the t
DT
delay is configured according to the
equation specified in the CTAR[DT] bitfield description. When in Continuous Clock
mode, the delay is fixed at 1 SCK period.
46.4.4 Transfer formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK)
signal and the PCS signals. The SCK signal provided by the master device synchronizes
shifting and sampling of the data on the SIN and SOUT pins. The PCS signals serve as
enable signals for the slave devices.
In Master mode, the CPOL and CPHA bits in the Clock and Transfer Attributes Registers
(CTARn) select the polarity and phase of the serial clock, SCK.
• CPOL - Selects the idle state polarity of the SCK
• CPHA - Selects if the data on SOUT is valid before or on the first SCK edge
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1216
Preliminary
Freescale Semiconductor, Inc.
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