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When the CONT bit = 0, the module drives the asserted Chip Select signals to their idle
states in between frames. The idle states of the Chip Select signals are selected by the
PCSISn bits in the MCR. The following timing diagram is for two four-bit transfers with
CPHA = 1 and CONT = 0.
PCSx
SCK
Master SIN
t
CSC =
PCS to SCK dela
t
ASC =
After SCK delay
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
DT =
Delay after Transfer (minimum CS negation time)
t
CSC
t
ASC
t
CSC
t
DT
Figure 46-73. Example of non-continuous format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two
transfers. The Delay between Transfers (t
DT
) is not inserted between the transfers. The
following figure shows the timing diagram for two four-bit transfers with CPHA = 1 and
CONT = 1.
PCS
Master SIN
tCSC
=
P
C
S
to SCK del ay
t
ASC
=
After SCK delay
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
CSC
t
ASC
t
CSC
Figure 46-74. Example of continuous transfer (CPHA=1, CONT=1)
When using the module with continuous selection follow these rules:
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1220
Preliminary
Freescale Semiconductor, Inc.
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