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• Continuous SCK with CONT bit set and entering Stopped state (refer to Start and
Stop of module transfers).
• Continuous SCK with CONT bit set and entering Stop mode or Module Disable
mode.
The following figure shows timing diagram for Continuous SCK format with Continuous
Selection enabled.
PCS
Master SIN
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
transfer 1 transfer 2
Figure 46-76. Continuous SCK timing diagram (CONT=1)
46.4.6 Slave Mode Operation Constraints
Slave mode logic shift register is buffered. This allows data streaming operation, when
the DSPI is permanently selected and data is shifted in with a constant rate.
The transmit data is transferred at second SCK clock edge of the each frame to the shift
register if the SS signal is asserted and any time when transmit data is ready and SS
signal is negated.
Received data is transferred to the receive buffer at last SCK edge of each frame, defined
by frame size programmed to the CTAR0/1 register. Then the data from the buffer is
transferred to the RXFIFO or DDR register.
If the
SS negates before that last SCK edge, the data from shift register is lost.
46.4.7 Interrupts/DMA requests
The module has several conditions that can generate only interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Chapter 46 Serial Peripheral Interface (SPI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1223
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