Information

Push TX FIFO Register
Transmit Next
Data Pointer
Shift Register
SOUT
+1
-1
TX FIFO Counter
TX FIFO Base
-
Entry C
Entry A (first in)
Entry D (last in)
Entry B
-
-
-
Figure 46-77. TX FIFO pointers and counter
46.5.6.1 Address Calculation for the First-in Entry and Last-in Entry
in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following
equation:
The memory address of the last-in entry in the TX FIFO is computed by the following
equation:
TX FIFO Base - Base address of TX FIFO
TXCTR - TX FIFO Counter
TXNXTPTR - Transmit Next Pointer
TX FIFO Depth - Transmit FIFO depth, implementation specific
46.5.6.2 Address Calculation for the First-in Entry and Last-in Entry
in the RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following
equation:
Chapter 46 Serial Peripheral Interface (SPI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1231
General Business Information