Information

48.3 Memory map and registers
This section provides a detailed description of all memory and registers.
Accessing reserved addresses within the memory map results in a transfer error. None of
the contents of the implemented addresses are modified as a result of that access.
Only byte accesses are supported.
UART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A000 UART Baud Rate Registers: High (UART0_BDH) 8 R/W 00h 48.3.1/1280
4006_A001 UART Baud Rate Registers: Low (UART0_BDL) 8 R/W 04h 48.3.2/1281
4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h 48.3.3/1282
4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h 48.3.4/1283
4006_A004 UART Status Register 1 (UART0_S1) 8 R C0h 48.3.5/1285
4006_A005 UART Status Register 2 (UART0_S2) 8 R/W 00h 48.3.6/1288
4006_A006 UART Control Register 3 (UART0_C3) 8 R/W 00h 48.3.7/1290
4006_A007 UART Data Register (UART0_D) 8 R/W 00h 48.3.8/1291
4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h 48.3.9/1292
4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h
48.3.10/
1293
4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 00h
48.3.11/
1293
4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h
48.3.12/
1294
4006_A00C UART Extended Data Register (UART0_ED) 8 R 00h
48.3.13/
1295
4006_A00D UART Modem Register (UART0_MODEM) 8 R/W 00h
48.3.14/
1296
4006_A00E UART Infrared Register (UART0_IR) 8 R/W 00h
48.3.15/
1297
4006_A010 UART FIFO Parameters (UART0_PFIFO) 8 R/W See section
48.3.16/
1298
4006_A011 UART FIFO Control Register (UART0_CFIFO) 8 R/W 00h
48.3.17/
1299
4006_A012 UART FIFO Status Register (UART0_SFIFO) 8 R/W C0h
48.3.18/
1300
4006_A013 UART FIFO Transmit Watermark (UART0_TWFIFO) 8 R/W 00h
48.3.19/
1301
4006_A014 UART FIFO Transmit Count (UART0_TCFIFO) 8 R 00h
48.3.20/
1302
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1270
Preliminary
Freescale Semiconductor, Inc.
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