Information
UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A015 UART FIFO Receive Watermark (UART0_RWFIFO) 8 R/W 01h
48.3.21/
1302
4006_A016 UART FIFO Receive Count (UART0_RCFIFO) 8 R 00h
48.3.22/
1303
4006_A018 UART 7816 Control Register (UART0_C7816) 8 R/W 00h
48.3.23/
1303
4006_A019 UART 7816 Interrupt Enable Register (UART0_IE7816) 8 R/W 00h
48.3.24/
1305
4006_A01A UART 7816 Interrupt Status Register (UART0_IS7816) 8 R/W 00h
48.3.25/
1306
4006_A01B UART 7816 Wait Parameter Register (UART0_WP7816T0) 8 R/W 0Ah
48.3.26/
1307
4006_A01B UART 7816 Wait Parameter Register (UART0_WP7816T1) 8 R/W 0Ah
48.3.27/
1308
4006_A01C UART 7816 Wait N Register (UART0_WN7816) 8 R/W 00h
48.3.28/
1308
4006_A01D UART 7816 Wait FD Register (UART0_WF7816) 8 R/W 01h
48.3.29/
1309
4006_A01E UART 7816 Error Threshold Register (UART0_ET7816) 8 R/W 00h
48.3.30/
1309
4006_A01F UART 7816 Transmit Length Register (UART0_TL7816) 8 R/W 00h
48.3.31/
1310
4006_A021 UART CEA709.1-B Control Register 6 (UART0_C6) 8 R/W 00h
48.3.32/
1311
4006_A022
UART CEA709.1-B Packet Cycle Time Counter High
(UART0_PCTH)
8 R/W 00h
48.3.33/
1311
4006_A023
UART CEA709.1-B Packet Cycle Time Counter Low
(UART0_PCTL)
8 R/W 00h
48.3.34/
1312
4006_A024 UART CEA709.1-B Beta1 Timer (UART0_B1T) 8 R/W 00h
48.3.35/
1312
4006_A025
UART CEA709.1-B Secondary Delay Timer High
(UART0_SDTH)
8 R/W 00h
48.3.36/
1313
4006_A026
UART CEA709.1-B Secondary Delay Timer Low
(UART0_SDTL)
8 R/W 00h
48.3.37/
1313
4006_A027 UART CEA709.1-B Preamble (UART0_PRE) 8 R/W 00h
48.3.38/
1313
4006_A028 UART CEA709.1-B Transmit Packet Length (UART0_TPL) 8 R/W 00h
48.3.39/
1314
4006_A029 UART CEA709.1-B Interrupt Enable Register (UART0_IE) 8 R/W 00h
48.3.40/
1314
4006_A02A UART CEA709.1-B WBASE (UART0_WB) 8 R/W 00h
48.3.41/
1315
4006_A02B UART CEA709.1-B Status Register (UART0_S3) 8 R/W 00h
48.3.42/
1316
Table continues on the next page...
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1271
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