Information
UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_B02C UART CEA709.1-B Status Register (UART1_S4) 8 R/W 00h
48.3.43/
1317
4006_B02D UART CEA709.1-B Received Packet Length (UART1_RPL) 8 R 00h
48.3.44/
1318
4006_B02E
UART CEA709.1-B Received Preamble Length
(UART1_RPREL)
8 R 00h
48.3.45/
1319
4006_B02F UART CEA709.1-B Collision Pulse Width (UART1_CPW) 8 R/W 00h
48.3.46/
1319
4006_B030
UART CEA709.1-B Receive Indeterminate Time
(UART1_RIDT)
8 R/W 00h
48.3.47/
1319
4006_B031
UART CEA709.1-B Transmit Indeterminate Time
(UART1_TIDT)
8 R/W 00h
48.3.48/
1320
4006_C000 UART Baud Rate Registers: High (UART2_BDH) 8 R/W 00h 48.3.1/1280
4006_C001 UART Baud Rate Registers: Low (UART2_BDL) 8 R/W 04h 48.3.2/1281
4006_C002 UART Control Register 1 (UART2_C1) 8 R/W 00h 48.3.3/1282
4006_C003 UART Control Register 2 (UART2_C2) 8 R/W 00h 48.3.4/1283
4006_C004 UART Status Register 1 (UART2_S1) 8 R C0h 48.3.5/1285
4006_C005 UART Status Register 2 (UART2_S2) 8 R/W 00h 48.3.6/1288
4006_C006 UART Control Register 3 (UART2_C3) 8 R/W 00h 48.3.7/1290
4006_C007 UART Data Register (UART2_D) 8 R/W 00h 48.3.8/1291
4006_C008 UART Match Address Registers 1 (UART2_MA1) 8 R/W 00h 48.3.9/1292
4006_C009 UART Match Address Registers 2 (UART2_MA2) 8 R/W 00h
48.3.10/
1293
4006_C00A UART Control Register 4 (UART2_C4) 8 R/W 00h
48.3.11/
1293
4006_C00B UART Control Register 5 (UART2_C5) 8 R/W 00h
48.3.12/
1294
4006_C00C UART Extended Data Register (UART2_ED) 8 R 00h
48.3.13/
1295
4006_C00D UART Modem Register (UART2_MODEM) 8 R/W 00h
48.3.14/
1296
4006_C00E UART Infrared Register (UART2_IR) 8 R/W 00h
48.3.15/
1297
4006_C010 UART FIFO Parameters (UART2_PFIFO) 8 R/W See section
48.3.16/
1298
4006_C011 UART FIFO Control Register (UART2_CFIFO) 8 R/W 00h
48.3.17/
1299
4006_C012 UART FIFO Status Register (UART2_SFIFO) 8 R/W C0h
48.3.18/
1300
4006_C013 UART FIFO Transmit Watermark (UART2_TWFIFO) 8 R/W 00h
48.3.19/
1301
4006_C014 UART FIFO Transmit Count (UART2_TCFIFO) 8 R 00h
48.3.20/
1302
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1274
Preliminary
Freescale Semiconductor, Inc.
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