Information
UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_C02C UART CEA709.1-B Status Register (UART2_S4) 8 R/W 00h
48.3.43/
1317
4006_C02D UART CEA709.1-B Received Packet Length (UART2_RPL) 8 R 00h
48.3.44/
1318
4006_C02E
UART CEA709.1-B Received Preamble Length
(UART2_RPREL)
8 R 00h
48.3.45/
1319
4006_C02F UART CEA709.1-B Collision Pulse Width (UART2_CPW) 8 R/W 00h
48.3.46/
1319
4006_C030
UART CEA709.1-B Receive Indeterminate Time
(UART2_RIDT)
8 R/W 00h
48.3.47/
1319
4006_C031
UART CEA709.1-B Transmit Indeterminate Time
(UART2_TIDT)
8 R/W 00h
48.3.48/
1320
4006_D000 UART Baud Rate Registers: High (UART3_BDH) 8 R/W 00h 48.3.1/1280
4006_D001 UART Baud Rate Registers: Low (UART3_BDL) 8 R/W 04h 48.3.2/1281
4006_D002 UART Control Register 1 (UART3_C1) 8 R/W 00h 48.3.3/1282
4006_D003 UART Control Register 2 (UART3_C2) 8 R/W 00h 48.3.4/1283
4006_D004 UART Status Register 1 (UART3_S1) 8 R C0h 48.3.5/1285
4006_D005 UART Status Register 2 (UART3_S2) 8 R/W 00h 48.3.6/1288
4006_D006 UART Control Register 3 (UART3_C3) 8 R/W 00h 48.3.7/1290
4006_D007 UART Data Register (UART3_D) 8 R/W 00h 48.3.8/1291
4006_D008 UART Match Address Registers 1 (UART3_MA1) 8 R/W 00h 48.3.9/1292
4006_D009 UART Match Address Registers 2 (UART3_MA2) 8 R/W 00h
48.3.10/
1293
4006_D00A UART Control Register 4 (UART3_C4) 8 R/W 00h
48.3.11/
1293
4006_D00B UART Control Register 5 (UART3_C5) 8 R/W 00h
48.3.12/
1294
4006_D00C UART Extended Data Register (UART3_ED) 8 R 00h
48.3.13/
1295
4006_D00D UART Modem Register (UART3_MODEM) 8 R/W 00h
48.3.14/
1296
4006_D00E UART Infrared Register (UART3_IR) 8 R/W 00h
48.3.15/
1297
4006_D010 UART FIFO Parameters (UART3_PFIFO) 8 R/W See section
48.3.16/
1298
4006_D011 UART FIFO Control Register (UART3_CFIFO) 8 R/W 00h
48.3.17/
1299
4006_D012 UART FIFO Status Register (UART3_SFIFO) 8 R/W C0h
48.3.18/
1300
4006_D013 UART FIFO Transmit Watermark (UART3_TWFIFO) 8 R/W 00h
48.3.19/
1301
4006_D014 UART FIFO Transmit Count (UART3_TCFIFO) 8 R 00h
48.3.20/
1302
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1276
Preliminary
Freescale Semiconductor, Inc.
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