Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_D02C UART CEA709.1-B Status Register (UART3_S4) 8 R/W 00h
48.3.43/
1317
4006_D02D UART CEA709.1-B Received Packet Length (UART3_RPL) 8 R 00h
48.3.44/
1318
4006_D02E
UART CEA709.1-B Received Preamble Length
(UART3_RPREL)
8 R 00h
48.3.45/
1319
4006_D02F UART CEA709.1-B Collision Pulse Width (UART3_CPW) 8 R/W 00h
48.3.46/
1319
4006_D030
UART CEA709.1-B Receive Indeterminate Time
(UART3_RIDT)
8 R/W 00h
48.3.47/
1319
4006_D031
UART CEA709.1-B Transmit Indeterminate Time
(UART3_TIDT)
8 R/W 00h
48.3.48/
1320
400E_A000 UART Baud Rate Registers: High (UART4_BDH) 8 R/W 00h 48.3.1/1280
400E_A001 UART Baud Rate Registers: Low (UART4_BDL) 8 R/W 04h 48.3.2/1281
400E_A002 UART Control Register 1 (UART4_C1) 8 R/W 00h 48.3.3/1282
400E_A003 UART Control Register 2 (UART4_C2) 8 R/W 00h 48.3.4/1283
400E_A004 UART Status Register 1 (UART4_S1) 8 R C0h 48.3.5/1285
400E_A005 UART Status Register 2 (UART4_S2) 8 R/W 00h 48.3.6/1288
400E_A006 UART Control Register 3 (UART4_C3) 8 R/W 00h 48.3.7/1290
400E_A007 UART Data Register (UART4_D) 8 R/W 00h 48.3.8/1291
400E_A008 UART Match Address Registers 1 (UART4_MA1) 8 R/W 00h 48.3.9/1292
400E_A009 UART Match Address Registers 2 (UART4_MA2) 8 R/W 00h
48.3.10/
1293
400E_A00A UART Control Register 4 (UART4_C4) 8 R/W 00h
48.3.11/
1293
400E_A00B UART Control Register 5 (UART4_C5) 8 R/W 00h
48.3.12/
1294
400E_A00C UART Extended Data Register (UART4_ED) 8 R 00h
48.3.13/
1295
400E_A00D UART Modem Register (UART4_MODEM) 8 R/W 00h
48.3.14/
1296
400E_A00E UART Infrared Register (UART4_IR) 8 R/W 00h
48.3.15/
1297
400E_A010 UART FIFO Parameters (UART4_PFIFO) 8 R/W See section
48.3.16/
1298
400E_A011 UART FIFO Control Register (UART4_CFIFO) 8 R/W 00h
48.3.17/
1299
400E_A012 UART FIFO Status Register (UART4_SFIFO) 8 R/W C0h
48.3.18/
1300
400E_A013 UART FIFO Transmit Watermark (UART4_TWFIFO) 8 R/W 00h
48.3.19/
1301
400E_A014 UART FIFO Transmit Count (UART4_TCFIFO) 8 R 00h
48.3.20/
1302
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1278
Preliminary
Freescale Semiconductor, Inc.
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