Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400E_A02C UART CEA709.1-B Status Register (UART4_S4) 8 R/W 00h
48.3.43/
1317
400E_A02D UART CEA709.1-B Received Packet Length (UART4_RPL) 8 R 00h
48.3.44/
1318
400E_A02E
UART CEA709.1-B Received Preamble Length
(UART4_RPREL)
8 R 00h
48.3.45/
1319
400E_A02F UART CEA709.1-B Collision Pulse Width (UART4_CPW) 8 R/W 00h
48.3.46/
1319
400E_A030
UART CEA709.1-B Receive Indeterminate Time
(UART4_RIDT)
8 R/W 00h
48.3.47/
1319
400E_A031
UART CEA709.1-B Transmit Indeterminate Time
(UART4_TIDT)
8 R/W 00h
48.3.48/
1320
48.3.1 UART Baud Rate Registers: High (UARTx_BDH)
This register, along with the BDL register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written.
BDL is reset to a nonzero value, but after reset, the baud rate generator remains disabled
until the first time the receiver or transmitter is enabled, that is, when C2[RE] or C2[TE]
is set.
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read
LBKDIE RXEDGIE
0
SBR
Write
Reset
0 0 0 0 0 0 0 0
UARTx_BDH field descriptions
Field Description
7
LBKDIE
LIN Break Detect Interrupt Enable
Enables the LIN break detect flag, LBKDIF, to generate interrupt requests based on the state of
LBKDDMAS.
0 LBKDIF interrupt requests disabled.
1
LBKDIF interrupt requests enabled.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable
Enables the receive input active edge, RXEDGIF, to generate interrupt requests.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1280
Preliminary
Freescale Semiconductor, Inc.
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