Information

UARTx_BDH field descriptions (continued)
Field Description
0 Hardware interrupts from RXEDGIF disabled using polling.
1 RXEDGIF interrupt request enabled.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4–0
SBR
UART Baud Rate Bits
The baud rate for the UART is determined by the 13 SBR fields. See Baud rate generation for details.
NOTE: The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after
reset.The baud rate generator is disabled when SBR = 0.
Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data
in a temporary location until BDL is written.
48.3.2 UART Baud Rate Registers: Low (UARTx_BDL)
This register, along with the BDH register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting, SBR[12:0], first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written. BDL is reset to a nonzero value, but after reset, the
baud rate generator remains disabled until the first time the receiver or transmitter is
enabled, that is, when C2[RE] or C2[TE] is set.
Address: Base address + 1h offset
Bit 7 6 5 4 3 2 1 0
Read
SBR
Write
Reset
0 0 0 0 0 1 0 0
UARTx_BDL field descriptions
Field Description
7–0
SBR
UART Baud Rate Bits
The baud rate for the UART is determined by the 13 SBR fields. See Baud rate generation for details.
NOTE: The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after
reset.The baud rate generator is disabled when SBR = 0.
Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data
in a temporary location until BDL is written.
When the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate fields must
be even, the least significant bit is 0. See MODEM register for more details.
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1281
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