Information
UARTx_C1 field descriptions (continued)
Field Description
NOTE: • In case the UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after a
received stop bit, therefore resetting the idle count.
• In case the UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT has
no effect on when the receiver starts counting logic 1s as idle character bits. In idle line
wakeup, an idle character is recognized at anytime the receiver sees 10, 11, or 12 1s
depending on the M, PE, and C4[M10] fields.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This field must be set when C7816[ISO_7816E] is set/enabled.
0 Parity function disabled.
1 Parity function enabled.
0
PT
Parity Type
Determines whether the UART generates and checks for even parity or odd parity. With even parity, an
even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd
number of 1s clears the parity bit and an even number of 1s sets the parity bit. This field must be cleared
when C7816[ISO_7816E] is set/enabled.
0 Even parity.
1 Odd parity.
48.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base address + 3h offset
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C2 field descriptions
Field Description
7
TIE
Transmitter Interrupt or DMA Transfer Enable.
Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, based on the state of
C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be written
unless servicing a DMA request.
0 TDRE interrupt and DMA transfer requests disabled.
1 TDRE interrupt or DMA transfer requests enabled.
Table continues on the next page...
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1283
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