Information

UARTx_S2 field descriptions (continued)
Field Description
NOTE: In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible to configure the guard time
to 12. However, if a NACK is required to be transmitted, the data transfer actually takes 13 ETU
with the 13th ETU slot being a inactive buffer. Therefore, in this situation, the RAF may deassert
one ETU prior to actually being inactive.
0 UART receiver idle/inactive waiting for a start bit.
1 UART receiver active, RxD input not idle.
48.3.7 UART Control Register 3 (UARTx_C3)
Writing R8 does not have any effect. TXDIR and TXINV can be changed only between
transmit and receive packets.
Address: Base address + 6h offset
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8
Received Bit 8
R8 is the ninth data bit received when the UART is configured for 9-bit data format, that is, if C1[M] = 1 or
C4[M10] = 1.
6
T8
Transmit Bit 8
T8 is the ninth data bit transmitted when the UART is configured for 9-bit data format, that is, if C1[M] = 1
or C4[M10] = 1.
NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.
The same value is transmitted until T8 is rewritten.
5
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
Determines whether the TXD pin is used as an input or output in the single-wire mode of operation. This
field is relevant only to the single wire mode. When C7816[ISO7816E] is set/enabled and C7816[TTYPE]
= 1, this field is automatically cleared after the requested block is transmitted. This condition is detected
when TL7816[TLEN] = 0 and 4 additional characters are transmitted. Additionally, if C7816[ISO7816E] is
set/enabled and C7816[TTYPE] = 0 and a NACK is being transmitted, the hardware automatically
overrides this field as needed. In this situation, TXDIR does not reflect the temporary state associated with
the NACK.
0 TXD pin is an input in single wire mode.
1 TXD pin is an output in single wire mode.
4
TXINV
Transmit Data Inversion.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1290
Preliminary
Freescale Semiconductor, Inc.
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