Information

UARTx_C3 field descriptions (continued)
Field Description
Setting this field reverses the polarity of the transmitted data output. In NRZ format, a one is represented
by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity.
In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a
one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining
idle high for a one for inverted polarity.This field is automatically set when C7816[INIT] and
C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
NOTE: Setting TXINV inverts all transmitted values, including idle, break, start, and stop bits. In loop
mode, if TXINV is set, the receiver gets the transmit inversion bit when RXINV is disabled. When
C7816[ISO7816E] is set/enabled then only the transmitted data bits and parity bit are inverted.
0 Transmit data is not inverted.
1 Transmit data is inverted.
3
ORIE
Overrun Error Interrupt Enable
Enables the overrun error flag, S1[OR], to generate interrupt requests.
0 OR interrupts are disabled.
1 OR interrupt requests are enabled.
2
NEIE
Noise Error Interrupt Enable
Enables the noise flag, S1[NF], to generate interrupt requests.
0 NF interrupt requests are disabled.
1 NF interrupt requests are enabled.
1
FEIE
Framing Error Interrupt Enable
Enables the framing error flag, S1[FE], to generate interrupt requests.
0 FE interrupt requests are disabled.
1 FE interrupt requests are enabled.
0
PEIE
Parity Error Interrupt Enable
Enables the parity error flag, S1[PF], to generate interrupt requests.
0 PF interrupt requests are disabled.
1 PF interrupt requests are enabled.
48.3.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data register and writes go to the write-only transmit data register.
NOTE
• In 8-bit or 9-bit data format, only UART data register (D)
needs to be accessed to clear the S1[RDRF] bit (assuming
receiver buffer level is less than RWFIFO[RXWATER]).
The C3 register needs to be read, prior to the D register,
only if the ninth bit of data needs to be captured. Similarly,
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1291
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