Information

UARTx_PCTH field descriptions
Field Description
7–0
PCTH
Packet Cycle Time Counter High
Indicates the most significant byte of maximum period after the line code violation for which the bus could
remain idle without decrementing back log count. If the time elapsed after line code violation is greater
than packet cycle time, then packet cycle timer expired interrupt is generated. It is measured in terms of bit
times, that is, the time it takes for a single bit or one differential Manchester symbol to be transmitted. This
is medium dependent and hence does not usually require adjustment and is programmed only once.
48.3.34 UART CEA709.1-B Packet Cycle Time Counter Low
(UARTx_PCTL)
Address: Base address + 23h offset
Bit 7 6 5 4 3 2 1 0
Read
PCTL
Write
Reset
0 0 0 0 0 0 0 0
UARTx_PCTL field descriptions
Field Description
7–0
PCTL
Packet Cycle Time Counter Low
Indicates the least significant byte of maximum period after the line code violation for which the bus could
remain idle without decrementing back log count. If the time elapsed after line code violation is greater
than packet cycle time, then packet cycle timer expired interrupt is generated. It is measured in terms of bit
times, that is, the time it takes for a single bit or one Differential Manchester symbol to be transmitted. This
is medium dependent and therefore does not usually require adjustment and is programmed only once.
48.3.35 UART CEA709.1-B Beta1 Timer (UARTx_B1T)
Address: Base address + 24h offset
Bit 7 6 5 4 3 2 1 0
Read
B1T
Write
Reset
0 0 0 0 0 0 0 0
UARTx_B1T field descriptions
Field Description
7–0
B1T
Beta1 Timer
Beta1 delay is a value that is system dependent and usually does not require adjustment. It is
programmed only once and measured in bit times.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1312
Preliminary
Freescale Semiconductor, Inc.
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