Information

48.3.36 UART CEA709.1-B Secondary Delay Timer High
(UARTx_SDTH)
Address: Base address + 25h offset
Bit 7 6 5 4 3 2 1 0
Read
SDTH
Write
Reset
0 0 0 0 0 0 0 0
UARTx_SDTH field descriptions
Field Description
7–0
SDTH
Secondary Delay Timer High
This is the most significant byte of the secondary delay timer and is set by software. This is generally a
variable value that must be set for each data message to be transmitted. It is measured in bit times, that
is, the time that it takes for a single bit or one differential Manchester symbol to be transmitted. This value
must be between 0 and (BL*Wbase) + (ProritySlots -1), Beta2 timeslots. A value of zero indicates that the
queued packet will be sent immediately upon expiration of the beta1 timer.
48.3.37 UART CEA709.1-B Secondary Delay Timer Low
(UARTx_SDTL)
Address: Base address + 26h offset
Bit 7 6 5 4 3 2 1 0
Read
SDTL
Write
Reset
0 0 0 0 0 0 0 0
UARTx_SDTL field descriptions
Field Description
7–0
SDTL
Secondary Delay Timer Low
This is the least significant byte of the secondary delay timer and is set by software. This is generally a
variable value that must be set for each data message to be transmitted. It is measured in bit times, that
is, the time that it takes for a single bit or one Differential Manchester symbol to be transmitted. This value
must be between 0 and (BL*Wbase) + (ProritySlots -1), Beta2 timeslots. A value of zero indicates that the
queued packet will be sent immediately upon expiration of the Beta1 timer.
48.3.38 UART CEA709.1-B Preamble (UARTx_PRE)
Address: Base address + 27h offset
Bit 7 6 5 4 3 2 1 0
Read
PREAMBLE
Write
Reset
0 0 0 0 0 0 0 0
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1313
General Business Information