Information

UARTx_IE field descriptions (continued)
Field Description
NOTE: This field cannot be cleared except by disabling CEA709. Therefore, ISDIE must be cleared when
the first initial sync detection interrupt occurs. If the ISD interrupt is not disabled in the interrupt
handler, then user will continuously get interrupts.
0 Interrupt is disabled.
1 Interrupt is enabled.
4
PRXIE
Packet Received Interrupt Enable
Interrupt enable for packet received flag.
0 Interrupt is disabled.
1 Interrupt is enabled.
3
PTXIE
Packet Transmitted Interrupt Enable
Interrupt enable for packet transmitted flag.
0 Interrupt is disabled.
1 Interrupt is enabled.
2
PCTEIE
Packet Cycle Timer Interrupt Enable
Interrupt enable for packet cycle time expired flag.
0 Interrupt is disabled.
1 Interrupt is enabled.
1
PSIE
Preamble Start Interrupt Enable
Interrupt enable for preamble start flag.
0 Interrupt is disabled.
1 Interrupt is enabled.
0
TXFIE
Transmission Fail Interrupt Enable
Interrupt enable for transmission fail flag.
0 Interrupt is disabled.
1 Interrupt is enabled.
48.3.41 UART CEA709.1-B WBASE (UARTx_WB)
Address: Base address + 2Ah offset
Bit 7 6 5 4 3 2 1 0
Read
WBASE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_WB field descriptions
Field Description
7–0
WBASE
CEA709.1-B WBASE register
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1315
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