Information

48.3.45 UART CEA709.1-B Received Preamble Length
(UARTx_RPREL)
Address: Base address + 2Eh offset
Bit 7 6 5 4 3 2 1 0
Read RPREL
Write
Reset
0 0 0 0 0 0 0 0
UARTx_RPREL field descriptions
Field Description
7–0
RPREL
Received Preamble Length
Indicates the number of bit sync fields received in the preamble.
48.3.46 UART CEA709.1-B Collision Pulse Width (UARTx_CPW)
Address: Base address + 2Fh offset
Bit 7 6 5 4 3 2 1 0
Read
CPW
Write
Reset
0 0 0 0 0 0 0 0
UARTx_CPW field descriptions
Field Description
7–0
CPW
CEA709.1-B CPW register
Indicates the width of valid collision pulse in terms of IPG clock cycles.
48.3.47 UART CEA709.1-B Receive Indeterminate Time
(UARTx_RIDT)
Address: Base address + 30h offset
Bit 7 6 5 4 3 2 1 0
Read
RIDT
Write
Reset
0 0 0 0 0 0 0 0
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1319
General Business Information