Information

Table 3-58. Reference links to related information (continued)
Topic Related module Reference
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.9.2.1 Reset value of MDIS bit
The CAN_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled
following a reset.
3.9.2.2 Number of message buffers
Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.
3.9.2.3 FlexCAN Clocking
3.9.2.3.1 Clocking Options
The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between
clocking the FlexCAN from the internal bus clock or the input clock (EXTAL).
3.9.2.3.2 Clock Gating
The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits.
These bits are cleared after any reset, which disables the clock to the corresponding
module. The appropriate clock enable bit should be set by software at the beginning of
the FlexCAN initialization routine to enable the module clock before attempting to
initialize any of the FlexCAN registers.
3.9.2.4 FlexCAN Interrupts
The FlexCAN has multiple sources of interrupt requests. However, some of these sources
are OR'd together to generate a single interrupt request. See below for the mapping of the
individual interrupt sources to the interrupt request:
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
133
General Business Information