Information

preamble completes, the preamble started interrupt is asserted when the UART starts

transmitting the preamble.

NOTE

If the data buffer does not contain at least one byte of valid data

and the transmit packet length register has been updated prior to

the preamble completing, an underflow event will occur and

TXEN is deasserted. The packet is terminated by transmitting

line code violation.

48.4.1.7 Collision detection

Collision flag is detected only when device is transmitting if C6[CE] is asserted. The

collision pulse is valid if it is asserted for CPW number of peripheral clock cycles. If the

collision signal is already asserted before the start of packet transmission, then the width

of the collision pulse is calculated from the start of transmit packet as shown in the figure

below. If the collision signal is not cleared by the software by writing 11b, then the flag

continues to retain the previous value. After the flag is cleared, the collision pulse width

is calculated again, and the flag is asserted, if the width is equal to or more than the

programmed CPW value.

CPW

ipp_ind_collision

TX packet

collision flag

clr collision flag

Figure 48-293. Collision pulse detection

The collision signal is asynchronous to the ipg clk, therefore the collision pulse of width

exactly equal to CPW may not be detected correctly due to synchronization issue. The

collision pulse visible to design may be decreased by one peripheral clock cycle due to

the asynchronous nature of the collision pulse.

Functional description

K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

1330

Preliminary

Freescale Semiconductor, Inc.

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