Information

48.4.5.3.4 Nine-bit format with parity enabled
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
PARITY
STOP
BIT
START
BIT
START
BIT
Figure 48-306. Eight bits of data with LSB first and parity
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PARITY
STOP
BIT
START
BIT
START
BIT
Figure 48-307. Eight bits of data with MSB first and parity
48.4.5.3.5 Non-memory mapped tenth bit for parity
The most significant memory-mapped bit can be used for address mark wakeup.
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
PARITY
STOP
BIT
START
BIT
START
BIT
BIT 0
ADDRESS
MARK
Figure 48-308. Nine bits of data with LSB first and parity
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PARITY
STOP
BIT
START
BIT
START
BIT
BIT 8
ADDRESS
MARK
Figure 48-309. Nine bits of data with MSB first and parity
48.4.6 Single-wire operation
Normally, the UART uses two pins for transmitting and receiving. In single wire
operation, the RXD pin is disconnected from the UART and the UART implements a
half-duplex serial connection. The UART uses the TXD pin for both receiving and
transmitting.
RXD
Tx pin input
Tx pin output
TXINV
TRANSMITTER
RECEIVER
RXINV
Figure 48-310. Single-wire operation (C1[LOOPS] = 1, C1[RSRC] = 1)
Enable single wire operation by setting C1[LOOPS] and the receiver source field,
C1[RSRC]. Setting C1[LOOPS] disables the path from the unsynchronized receiver input
signal to the receiver. Setting C1[RSRC] connects the receiver input to the output of the
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1350
Preliminary
Freescale Semiconductor, Inc.
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