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3.9.3.4 TX FIFO size
Table 3-60. SPI transmit FIFO size
SPI Module Transmit FIFO size
SPI0 4
SPI1 4
3.9.3.5 RX FIFO Size
SPI supports up to 16-bit frame size during reception.
Table 3-61. SPI receive FIFO size
SPI Module Receive FIFO size
SPI0 4
SPI1 4
3.9.3.6 Number of PCS signals
The following table shows the number of peripheral chip select signals available per SPI
module.
Table 3-62. SPI PCS signals
SPI Module PCS Signals
SPI0 SPI_PCS[5:0]
SPI1 SPI_PCS[3:0]
3.9.3.7 SPI Operation in Low Power Modes
In VLPR and VLPW modes the SPI is functional; however, the reduced system
frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW
modes the max SPI_CLK frequency is 2MHz.
In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not
functional, but it is powered so that it retains state.
Communication interfaces
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
136
Preliminary
Freescale Semiconductor, Inc.
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