Information

49.1.3.3 Debug mode
In Debug mode, the SAI transmitter and/or receiver can continue operating provided the
Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug
mode is entered, the SAI is disabled after completing the current transmit or receive
frame. The transmitter and receiver bit clocks are not affected by Debug mode.
49.2 External signals
Name Function I/O Reset Pull
SAI_TX_BCLK Transmit Bit Clock I/O 0 —
SAI_TX_SYNC Transmit Frame Sync I/O 0 —
SAI_TX_DATA[1:0] Transmit Data O 0 —
SAI_RX_BCLK Receive Bit Clock I/O 0 —
SAI_RX_SYNC Receive Frame Sync I/O 0 —
SAI_RX_DATA[1:0] Receive Data I 0 —
SAI_MCLK Audio Master Clock I/O 0 —
49.3 Memory map and register definition
A read or write access to an address after the last register will result in a bus error.
I2S memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_F000 SAI Transmit Control Register (I2S0_TCSR) 32 R/W 0000_0000h 49.3.1/1373
4002_F004 SAI Transmit Configuration 1 Register (I2S0_TCR1) 32 R/W 0000_0000h 49.3.2/1376
4002_F008 SAI Transmit Configuration 2 Register (I2S0_TCR2) 32 R/W 0000_0000h 49.3.3/1376
4002_F00C SAI Transmit Configuration 3 Register (I2S0_TCR3) 32 R/W 0000_0000h 49.3.4/1378
4002_F010 SAI Transmit Configuration 4 Register (I2S0_TCR4) 32 R/W 0000_0000h 49.3.5/1379
4002_F014 SAI Transmit Configuration 5 Register (I2S0_TCR5) 32 R/W 0000_0000h 49.3.6/1380
4002_F020 SAI Transmit Data Register (I2S0_TDR0) 32
W
(always
reads 0)
0000_0000h 49.3.7/1381
4002_F024 SAI Transmit Data Register (I2S0_TDR1) 32
W
(always
reads 0)
0000_0000h 49.3.7/1381
4002_F040 SAI Transmit FIFO Register (I2S0_TFR0) 32 R 0000_0000h 49.3.8/1381
Table continues on the next page...
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1371
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