Information

I2S memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_F044 SAI Transmit FIFO Register (I2S0_TFR1) 32 R 0000_0000h 49.3.8/1381
4002_F060 SAI Transmit Mask Register (I2S0_TMR) 32 R/W 0000_0000h 49.3.9/1382
4002_F080 SAI Receive Control Register (I2S0_RCSR) 32 R/W 0000_0000h
49.3.10/
1383
4002_F084 SAI Receive Configuration 1 Register (I2S0_RCR1) 32 R/W 0000_0000h
49.3.11/
1386
4002_F088 SAI Receive Configuration 2 Register (I2S0_RCR2) 32 R/W 0000_0000h
49.3.12/
1386
4002_F08C SAI Receive Configuration 3 Register (I2S0_RCR3) 32 R/W 0000_0000h
49.3.13/
1388
4002_F090 SAI Receive Configuration 4 Register (I2S0_RCR4) 32 R/W 0000_0000h
49.3.14/
1389
4002_F094 SAI Receive Configuration 5 Register (I2S0_RCR5) 32 R/W 0000_0000h
49.3.15/
1390
4002_F0A0 SAI Receive Data Register (I2S0_RDR0) 32 R 0000_0000h
49.3.16/
1391
4002_F0A4 SAI Receive Data Register (I2S0_RDR1) 32 R 0000_0000h
49.3.16/
1391
4002_F0C0 SAI Receive FIFO Register (I2S0_RFR0) 32 R 0000_0000h
49.3.17/
1391
4002_F0C4 SAI Receive FIFO Register (I2S0_RFR1) 32 R 0000_0000h
49.3.17/
1391
4002_F0E0 SAI Receive Mask Register (I2S0_RMR) 32 R/W 0000_0000h
49.3.18/
1392
4002_F100 SAI MCLK Control Register (I2S0_MCR) 32 R/W 0000_0000h
49.3.19/
1392
4002_F104 SAI MCLK Divide Register (I2S0_MDR) 32 R/W 0000_0000h
49.3.20/
1393
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1372
Preliminary
Freescale Semiconductor, Inc.
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