Information

I2Sx_RCSR field descriptions (continued)
Field Description
0
FRDE
FIFO Request DMA Enable
Enables/disables DMA requests.
0 Disables the DMA request.
1 Enables the DMA request.
49.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)
Address: 4002_F000h base + 84h offset = 4002_F084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RFW
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR1 field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–0
RFW
Receive FIFO Watermark
Configures the watermark level for all enabled receiver channels.
49.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 88h offset = 4002_F088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SYNC BCS BCI MSEL BCP BCD
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DIV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR2 field descriptions
Field Description
31–30
SYNC
Synchronous Mode
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1386
Preliminary
Freescale Semiconductor, Inc.
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