Information

I2Sx_RCR2 field descriptions (continued)
Field Description
0 Bit clock is generated externally in Slave mode.
1 Bit clock is generated internally in Master mode.
23–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
DIV
Bit Clock Divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
49.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 8Ch offset = 4002_F08Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RCE
0
WDFL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR3 field descriptions
Field Description
31–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17–16
RCE
Receive Channel Enable
Enables the corresponding data channel for receive operation. A channel must be enabled before its FIFO
is accessed.
0 Receive data channel N is disabled.
1 Receive data channel N is enabled.
15–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4–0
WDFL
Word Flag Configuration
Configures which word the start of word flag is set. The value written should be one less than the word
number (for example, write zero to configure for the first word in the frame). When configured to a value
greater than the Frame Size field, then the start of word flag is never set.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1388
Preliminary
Freescale Semiconductor, Inc.
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