Information

49.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 90h offset = 4002_F090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
FRSZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SYWD
0
MF FSE
0
FSP FSD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR4 field descriptions
Field Description
31–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20–16
FRSZ
Frame Size
Configures the number of words in each frame. The value written must be one less than the number of
words in the frame. For example, write 0 for one word per frame. The maximum supported frame size is 2
words.
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–8
SYWD
Sync Width
Configures the length of the frame sync in number of bit clocks. The value written must be one less than
the number of bit clocks. For example, write 0 for the frame sync to assert for one bit clock only. The sync
width cannot be configured longer than the first word of the frame.
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
MF
MSB First
Specifies whether the LSB or the MSB is transmitted/received first.
0 LSB is transmitted/received first.
1 MSB is transmitted/received first.
3
FSE
Frame Sync Early
0 Frame sync asserts with the first bit of the frame.
1 Frame sync asserts one bit before the first bit of the frame.
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
FSP
Frame Sync Polarity
Configures the polarity of the frame sync.
Table continues on the next page...
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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