Information

49.3.18 SAI Receive Mask Register (I2Sx_RMR)
This register is double-buffered and updates:
1. When RCSR[RE] is first set
2. At the end of each frame
This allows the masked words in each frame to change from frame to frame.
Address: 4002_F000h base + E0h offset = 4002_F0E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RWM
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RMR field descriptions
Field Description
31–0
RWM
Receive Word Mask
Configures whether the receive word is masked (received data ignored and not written to receive FIFO) for
the corresponding word in the frame.
0 Word N is enabled.
1 Word N is masked.
49.3.19 SAI MCLK Control Register (I2Sx_MCR)
The MCLK Control Register (MCR) controls the clock source and direction of the audio
master clock.
Address: 4002_F000h base + 100h offset = 4002_F100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DUF
MOE
0
MICS
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1392
Preliminary
Freescale Semiconductor, Inc.
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