Information

Fractional
Clock
Divider
1
0
11
01
10
00
EXTAL
PLL_OUT
ALT_CLK
SYS_CLK
SAI_MOE
MCLK
MCLK_OUT
MCLK_IN
11
01
10
00
BUS_CLK
SAI_CLKMODE
Bit
Clock
Divider
1
0
BCLK_IN
SAI
BCLK_OUT
SAI_BCD
BCLK
SAI_FRACT/SAI_DIVIDE
SAI_MICS
MCLK (other SAIs)
CLKGEN
Figure 49-58. SAI master clock generation
49.4.1.2 Bit clock
The SAI transmitter and receiver support asynchronous free-running bit clocks that can
be generated internally from an audio master clock or supplied externally. There is also
the option for synchronous bit clock and frame sync operation between the receiver and
transmitter or between multiple SAI peripherals.
Externally generated bit clocks must be:
• Enabled before the SAI transmitter or receiver is enabled
• Disabled after the SAI transmitter or receiver is disabled and completes its current
frames
49.4.1.3 Bus clock
The bus clock is used by the control and configuration registers and to generate
synchronous interrupts and DMA requests.
49.4.2 SAI resets
The SAI is asynchronously reset on system reset. The SAI has a software reset and a
FIFO reset.
49.4.2.1 Software reset
The SAI transmitter includes a software reset that resets all transmitter internal logic,
including the bit clock generation, status flags, and FIFO pointers. It does not reset the
configuration registers. The software reset remains asserted until cleared by software.
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1395
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