Information

The SAI receiver includes a software reset that resets all receiver internal logic, including
the bit clock generation, status flags and FIFO pointers. It does not reset the configuration
registers. The software reset remains asserted until cleared by software.
49.4.2.2 FIFO reset
The SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to the
same value as the FIFO read pointer. This empties the FIFO contents and is to be used
after TCSR[FEF] is set, and before the FIFO is re-initialized and TCSR[FEF] is cleared.
The FIFO reset is asserted for one cycle only.
The SAI receiver includes a FIFO reset that synchronizes the FIFO read pointer to the
same value as the FIFO write pointer. This empties the FIFO contents and is to be used
after the RCSR[FEF] is set and any remaining data has been read from the FIFO, and
before the RCSR[FEF] is cleared. The FIFO reset is asserted for one cycle only.
49.4.3 Synchronous modes
The SAI transmitter and receiver can operate synchronously to each other.
49.4.3.1 Synchronous mode
The SAI transmitter and receiver can be configured to operate with synchronous bit clock
and frame sync.
If the transmitter bit clock and frame sync are to be used by both the transmitter and
receiver:
• The transmitter must be configured for asynchronous operation and the receiver for
synchronous operation.
• In synchronous mode, the receiver is enabled only when both the transmitter and
receiver are enabled.
• It is recommended that the transmitter is the last enabled and the first disabled.
If the receiver bit clock and frame sync are to be used by both the transmitter and
receiver:
• The receiver must be configured for asynchronous operation and the transmitter for
synchronous operation.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1396
Preliminary
Freescale Semiconductor, Inc.
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