Information

Section number Title Page
17.2 Memory map/register descriptions...............................................................................................................................345
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................346
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................346
17.2.3 Control Register (MCM_CR)......................................................................................................................347
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................349
18.1.1 Features........................................................................................................................................................349
18.2 Memory Map / Register Definition...............................................................................................................................350
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................351
18.2.2 Control Register (AXBS_CRSn).................................................................................................................354
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................356
18.3 Functional Description..................................................................................................................................................356
18.3.1 General operation.........................................................................................................................................356
18.3.2 Register coherency.......................................................................................................................................357
18.3.3 Arbitration....................................................................................................................................................358
18.4 Initialization/application information...........................................................................................................................361
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................363
19.1.1 Features........................................................................................................................................................363
19.1.2 General operation.........................................................................................................................................363
19.2 Memory map/register definition...................................................................................................................................364
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................366
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................368
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................373
19.3 Functional description...................................................................................................................................................378
19.3.1 Access support.............................................................................................................................................378
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
14
Preliminary
Freescale Semiconductor, Inc.
General Business Information