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50.1.3.1 Detailed signal description
Table 50-3. GPIO interface-detailed signal descriptions
Signal I/O Description
PORTA31–PORTA0
PORTB31–PORTB0
PORTC31–PORTC0
PORTD31–PORTD0
PORTE31–PORTE0
I/O General-purpose input/output
State meaning Asserted: The pin is logic 1.
Deasserted: The pin is logic 0.
Timing Assertion: When output, this
signal occurs on the rising-
edge of the system clock. For
input, it may occur at any time
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.
50.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
GPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F000 Port Data Output Register (GPIOA_PDOR) 32 R/W 0000_0000h 50.2.1/1407
400F_F004 Port Set Output Register (GPIOA_PSOR) 32
W
(always
reads 0)
0000_0000h 50.2.2/1407
400F_F008 Port Clear Output Register (GPIOA_PCOR) 32
W
(always
reads 0)
0000_0000h 50.2.3/1408
400F_F00C Port Toggle Output Register (GPIOA_PTOR) 32
W
(always
reads 0)
0000_0000h 50.2.4/1408
400F_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h 50.2.5/1409
400F_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h 50.2.6/1409
400F_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h 50.2.1/1407
Table continues on the next page...
Chapter 50 General-Purpose Input/Output (GPIO)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1405
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