Information

GPIO memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F110 Port Data Input Register (GPIOE_PDIR) 32 R 0000_0000h 50.2.5/1409
400F_F114 Port Data Direction Register (GPIOE_PDDR) 32 R/W 0000_0000h 50.2.6/1409
50.2.1 Port Data Output Register (GPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output
pins.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDO
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDOR field descriptions
Field Description
31–0
PDO
Port Data Output
Unimplemented pins for a particular device read as zero.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
50.2.2 Port Set Output Register (GPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTSO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PSOR field descriptions
Field Description
31–0
PTSO
Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.
Chapter 50 General-Purpose Input/Output (GPIO)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1407
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