Information

TSI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_511C Counter Register (TSI0_CNTR15) 32 R 0000_0000h 51.6.5/1426
4004_5120
Low-Power Channel Threshold register
(TSI0_THRESHOLD)
32 R/W 0000_0000h 51.6.6/1427
51.6.1 General Control and Status register (TSIx_GENCS)
Address: 4004_5000h base + 0h offset = 4004_5000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
LPCLKS
LPSCNITV NSCN PS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EOSF
OUTRGF
EXTERF
OVRF
0
SCNIP
TSIEN
TSIIE ERIE
ESO
R
0
Reserved
STM STPE
W
w1c
w1c
w1c w1c
SWTS
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_GENCS field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
LPCLKS
Low-Power Mode Clock Source Selection
This field can be changed only if the TSI module is disabled (TSIEN bit = 0).
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1418
Preliminary
Freescale Semiconductor, Inc.
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