Information

TSIx_PEN field descriptions (continued)
Field Description
0 The corresponding pin is not used by TSI.
1 The corresponding pin is used by TSI.
1
PEN1
Touch Sensing Input Pin Enable Register 1
0 The corresponding pin is not used by TSI.
1 The corresponding pin is used by TSI.
0
PEN0
Touch Sensing Input Pin Enable Register 0
0 The corresponding pin is not used by TSI.
1 The corresponding pin is used by TSI.
51.6.4 Wake-Up Channel Counter Register (TSIx_WUCNTR)
Address: 4004_5000h base + Ch offset = 4004_500Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 WUCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_WUCNTR field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
WUCNT
Touch Sensing Wake-Up Channel 16-bit Counter Value
51.6.5 Counter Register (TSIx_CNTRn)
Address: 4004_5000h base + 100h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CTN CTN1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_CNTRn field descriptions
Field Description
31–16
CTN
Touch Sensing Channel n 16-bit Counter Value
15–0
CTN1
Touch Sensing Channel n-1 16-bit Counter Value
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1426
Preliminary
Freescale Semiconductor, Inc.
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