Information

3.9.6.2.5 Clock gating and I
2
S/SAI initialization
The clock to the I
2
S/SAI module can be gated using a bit in the SIM. To minimize power
consumption, these bits are cleared after any reset, which disables the clock to the
corresponding module. The clock enable bit should be set by software at the beginning of
the module initialization routine to enable the module clock before initialization of any of
the I
2
S/SAI registers.
3.9.6.3 I
2
S/SAI operation in low power modes
3.9.6.3.1 Stop and very low power modes
In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered
from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might
underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth.
In VLPW and VLPR modes, the module is limited by the maximum bus clock
frequencies.
When operating from an internally generated bit clock or Audio Master Clock that is
disabled in stop modes:
In Stop mode, the transmitter is disabled after completing the current transmit frame, and,
the receiver is disabled after completing the current receive frame. Entry into Stop mode
is prevented–not acknowledged–while waiting for the transmitter and receiver to be
disabled at the end of the current frame.
3.10 Human-machine interfaces
3.10.1 GPIO configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Human-machine interfaces
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
144
Preliminary
Freescale Semiconductor, Inc.
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