Information

Section number Title Page
Chapter 20
Direct Memory Access Multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................381
20.1.1 Overview......................................................................................................................................................381
20.1.2 Features........................................................................................................................................................382
20.1.3 Modes of operation......................................................................................................................................382
20.2 External signal description............................................................................................................................................383
20.3 Memory map/register definition...................................................................................................................................383
20.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................384
20.4 Functional description...................................................................................................................................................385
20.4.1 DMA channels with periodic triggering capability......................................................................................385
20.4.2 DMA channels with no triggering capability...............................................................................................387
20.4.3 "Always enabled" DMA sources.................................................................................................................387
20.5 Initialization/application information...........................................................................................................................388
20.5.1 Reset.............................................................................................................................................................389
20.5.2 Enabling and configuring sources................................................................................................................389
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................393
21.1.1 Block diagram..............................................................................................................................................393
21.1.2 Block parts...................................................................................................................................................394
21.1.3 Features........................................................................................................................................................396
21.2 Modes of operation.......................................................................................................................................................397
21.3 Memory map/register definition...................................................................................................................................397
21.3.1 Control Register (DMA_CR).......................................................................................................................409
21.3.2 Error Status Register (DMA_ES)................................................................................................................410
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................412
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................415
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................417
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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